Bipolar transistor and method for producing same

ABSTRACT

This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.

The invention relates to a bi-polar transistor and a procedure for itsmanufacture.

BACKGROUND OF THE ART

An important domain of use of vertical bi-polar transistors arehigh-speed applications. In order to improve the efficiency oftransistors in the domain of highest speeds, the influence of parasiticcomponents, i.e., resistance and capacitance, must be reduced.Therefore, highly conductive connections between the metal contacts andthe active (inner) transistor region as well as a minimized passivetransistor surface are required.

In order to meet these requirements, laterally scaled, the so-called“double polysilicon technologies” are used in modem procedures tomanufacture vertical bi-polar transistors. Such technologies make itpossible to arrange the base contact and parts of the highly conductivepolysilicon connection between the contact and the inner base throughinsulated zones. However, these design advantages as compared with the“simple polysilicon technologies” are associated with such disadvantagesas additional process complexity and increased contact resistance. Thesedisadvantages arise in connection with the required etching of thepolysilicon in the active zone of the transistor, and the diffusion ofthe doping agents from the highly doped polysilicon layer into themonocrystal base zone. Since the polysilicon for the base is removedover the active transistor zone by means of a dry-etching procedure, andthere is no selectivity to the underlying monocrystal silicon, damageoccurs to the exposed silicon surface. The consequence is then roughnessof the surface, imperfections of the grid structure and penetration offoreign substances. Various procedures have been suggested to eliminatethese problems. For example, etching-stop layers are used to protect theemitter zone in order to resolve the problems with dry etching.Additional procedure and cost is required to guarantee theself-adjusting of,the emitter zone and the etching-stop layer.

The application of epitaxy processes has recently further improved thehigh-speed properties. In-situ doping is used during the deposition inorder to achieve smaller sizes of the base, i.e., smaller thickness ofthe base layer and smaller base layer resistance. An additional variancein achieving a certain resistance of the base layer and a current gainand, therefore, optimal high-speed properties is provided by thedeposition of heterogeneous layers.

The concept of the double polysilicon technology with an etching-stoplayer is also applied in the case of an epitaxially deposited base layerusing the so-called selective epitaxy. During the selective epitaxyprocess, the deposition conditions are such that the epitaxial growthoccurs only on uncovered semiconductor surface. If differential epitaxyis used, during which the silicon material is deposited both on thesemiconductor and the insulator zones, an inner base and the connectionto a base contact (base zone) located on the insulator zone can beproduced at the same time. This generally eliminates the need of anadditional polysilicon layer. The resulting quasi double polysiliconarrangement allows to simplify the process.

However, as compared with a full-fledged double polysilicon process weface a disadvantage consisting in the fact that the thickness of theepitaxy layer in the active transistor zone cannot be set independentlyfrom the thickness of the silicon layer in the base zone or on theinsulator zones. Due to the insufficient nucleation of the SiO₂ layerusually used as insulator, the polycrystal layer is usually thinner thanthe epitaxially grown layer. As for the epitaxy layer thickness, twodifferent requirements exist. Within the emitter zone, a sufficientlythin layer should be present between the highly doped emitter and thebase. A thicker layer is beneficial in the outer base zone to allow lowresistance of the base. The patent documentation U.S. Pat. No.5,137,840A describes differential epitaxy process in a UHVCVD system ata pressure between 1×10⁻⁴ and 1×10⁻² Torr and a constant depositiontemperature of 500-800° C. for the buffer layer.

The task of this invention is to propose a bi-polar transistor and aprocedure for its manufacture that eliminates the disadvantages ofconventional arrangements for a simple polysilicon technology withdifferential epitaxy for the manufacture of the base, in order tofurther improve especially the high-speed properties of a bi-polartransistor, to produce highly conductive connections between the metalcontacts and the active (inner) transistor region as well as a minimizedpassive transistor surface, and to simultaneously avoid any additionalprocess complexity and increased contact resistance.

SUMMARY OF THE INVENTION

This invention resolves the task in that, by creating suitable epitaxyprocess conditions, the polysilicon layer is deposited on the insulatorzone with a greater thickness than the epitaxy layer in the activetransistor zone. The greater thickness of the polysilicon layer ascompared to the epitaxial layer is achieved by using a very lowtemperature for the deposition of a part of or the entire buffer layer.Apart from using a polysilicon layer, this invention also includes thepossible use of an amorphous silicon layer. The use of a low temperaturefor the deposition allows a better nucleation of the insulator layer anda reduction of the idle time for the deposition. The deposition at avery low temperature allows a higher deposition rate for the polycrystalor amorphous layer as compared with the epitaxial layer. This allowsachieving a greater thickness on the insulator layer as compared withthe active transistor zone.

A simple polysilicon bi-polar transistor with an epitaxially made baseaccording to this invention allows a reduction of the outer baseresistance without having to accept a deterioration of the emitterproperties. Due to a continuous deposition of the inner and outer zonesno surface problems occur with the base.

BRIEF DESCRIPTION OF THE DRAWINGS

The characteristics of this invention follow from the claims as well asfrom the descriptions and the drawings. Each individual characteristicas well as several characteristics in various combinations representdesigns deserving patent protection and such protection is claimed.Design examples of this invention are illustrated by the drawings andare explained in more detail in the following text.

The drawings show:

FIG. 1 A schematic illustration of a bi-polar transistor

FIG. 2 A schematic illustration of a bi-polar transistor according toFIG. 1 during the manufacture.

DETAILED DESCRIPTION OF THE INVENTION

We will now describe this invention in connection with a simplepolysilicon process with an epitaxially made base.

FIG. 1 schematically shows a bi-polar transistor 10 according to thisinvention. A collector zone of conductivity type II is made onsemiconductor substrate zone 11 of conductivity type I. If the emitterand collector are e.g. n-conductive, the base is of a p-type or viceversa. There exist several known procedures that produce a suitablecollector doping. One of them is e.g. the design shown in FIG. 1 with ahighly doped buried layer 12 and a less doped epitaxy layer 13. Anotherversion is implanted retrogressive domains. In the example shown here, afield insulation zone 14 separates the bi-polar transistor from othercomponents not shown in FIG. 1, and also separates the collector zonefrom the active transistor zone. Other suitable insulation techniquesare also known such as spaced mesa arrangements. As an option, a shaftimplant 20 can be applied in order to reduce the resistance between thecontact layer 21 made of highly doped polysilicon and the buried layer12.

An epitaxy series of layers—consisting of the buffer layer 15, anin-situ doped base layer 16 of conductivity type I, and a cover layer17—covers the emitter region in the active transistor zone and at leasta part of the insulation zone. The epitaxy layer structured outside theactive transistor zone is covered with a dielectric 18. Of substantialimportance, from the point of view of this invention, is the applicationof a thick polycrystal layer 19 on the insulator zone. As a variant, anamorphous layer can be used instead of the polycrystal layer 19. Theparticular values of the thickness, doping agent content as well as thematerial composition of the base are to be selected depending on thedesired functions of the bi-polar transistor and are not subject to anyspecial requirements from the point of this invention. In the exampleshown, the base layer is made of silicon with a doping of 2×10¹⁸ cm⁻³,and is 40 nm thick. However, other material compositions and dopingprofiles can be used, too. The application of a thin cover layer 17 overthe base layer is possible but not essential for the present invention.The doping of the emitter in a monocrystal silicon is performed byout-diffusion of the doping agent 22 from the highly doped polysiliconcontact layer 21. The thickness of the deposited cover layer can betypically 50 nm.

While the buffer, base and cover layers grow on the silicon substrate inmonocrystal form, polycrystal layers 19 arise over the insulation zone14. The thickness of the deposited polycrystal layer is greater than thethickness of the monocrystal layer. Outside the polysilicon contactlayer 21, which overlaps the active transistor zone, the doping in thebase zone is additionally increased by implantation 23. The insulationlayer 24 separates the emitter, base, and collector contact. Metalcontacts for emitter 25, base 26 and collector 27 complete the design ofthe transistor.

In the following text, the manufacture of a bi-polar transistoraccording to this invention is described by means of two examples.

EXAMPLE 1

FIG. 2 shows the basic structure of the procedure according to thisinvention. A highly doped n-layer 12 is applied on a p-doped siliconsubstrate 11 after a photolithographic structuring and layer 12 issubsequently cured. Afterwards, a slightly doped n-layer 13 is depositedby epitaxy. Usual process steps define the active zone and produceinsulation zones 14 (e.g. LOCOS) in the remaining zones. First, thebuffer layer 15 is deposited by means of differential epitaxy at a verylow temperature. A typical example of the deposition temperature is 550°C. At this temperature, the nucleus formation on the insulator zone isimproved and the idle time is reduced. The deposition rate of thepolycrystal layer is greater than the deposition rate of the epitaxiallayer. Subsequently, the base layer 16 and the cover layer 17 aredeposited. As a result, the polycrystal layer 19 on the insulator isthicker than the monocrystal layer in the active transistor zone.

After the photolithographic structuring of a mask, the deposited siliconor polysilicon layers are removed in the area of the future transistorand base zones by means of a plasma etching procedure using an etchingstop on the insulation zone. A dielectric 18, preferably an oxide, issubsequently applied. By means of a photolithographic structuring of alacquer mask, the collector zone is now exposed and shaft implant 20 isintroduced. After removing this lacquer mask and structuring anotherlacquer mask, an oxide layer (dielectric 18) is etched, preferably in awet chemical process, in the collector zone and in the emitter zone. Theprocess continues with the deposition of an amorphous silicon layer.This layer can be doped in-situ by implantation during or after thedeposition. The emitter and collector zones are covered by means of alithographic procedure. In the remaining zones, the amorphous silicon isremoved by plasma etching with a stop on the SiO₂ layer. During thesubsequent implantation of the base zone, the emitter and collectorcontact zones are protected by the existing masking. After the maskingis removed and the arising surface is covered with an oxide, annealingis performed to cure the implantation damage and to form thepoly-emitter. The process is completed by opening contact apertures forthe emitter, base and collector and a standard metallization for thetransistor contacts.

EXAMPLE 2

FIG. 2 shows the basic structure of the procedure according to thisinvention. A highly doped n-layer 12 is applied on a p-doped siliconsubstrate 11 after a photolithographic structuring and layer 12 issubsequently cured. Afterwards, a slightly doped n-layer 13 is depositedby epitaxy. Usual process steps define the active zone and produceinsulation zones 14 (e.g. LOCOS) in the remaining zones. First, thebuffer layer 15 is deposited by differential epitaxy in two steps. Inthe first step, a very low temperature is used. A typical value for thetemperature used is 550° C. At this temperature, the nucleus formationon the insulator zone is improved and the idle time is reduced. Thedeposition rate of the polycrystal layer is greater than the depositionrate of the epitaxial layer. After the deposition of the first part ofthe buffer layer, the growth of the buffer layer continues at the sametemperature or also at an increased temperature (a typical temperatureis 650° C.). Subsequently, the base layer 16 and the cover layer 17 aredeposited. As a result, the polycrystal layer 19 on the insulator isthicker than the monocrystal layer in the active transistor zone.

After the photolithographic structuring of a mask, the deposited siliconor polysilicon layers are removed in the area of the future transistorand base zones by means of a plasma etching procedure using an etchingstop on the insulation zone. A dielectric 18, preferably an oxide, issubsequently applied. By means of a photolithographic structuring of alacquer mask, the collector zone is now exposed and shaft implant 20 isintroduced. After removing this lacquer mask and structuring anotherlacquer mask, an oxide layer (dielectric 18) is etched, preferably in awet chemical process, in the collector zone and in the emitter zone. Theprocess continues with the deposition of an amorphous silicon layer.This layer can be doped in-situ by implantation during or after thedeposition. The emitter and collector zones are covered by means of alithographic procedure. In the remaining zones, the amorphous silicon isremoved by plasma etching with a stop on the SiO₂ layer. After thearising surface is covered with an oxide, annealing is performed to curethe implantation damage and to form the poly-emitter. The process iscompleted by opening contact apertures for the emitter, base andcollector and a standard metallization for the transistor contacts.

The present invention has explained, by means of concrete examples, abi-polar transistor and a procedure for its manufacture. However, itmust be noted that the present invention is not restricted to thedetails of the description in the example designs, since alterations andchanges are also claimed within this patent, since especiallymodifications of this process such as hetero-epitaxy or the integrationin a bi-polar CMOS (BiCMOS) technology is also possible.

What is claimed is:
 1. A procedure for the manufacture of a bi-polartransistor by means of differential epitaxy, during which structuredzones consisting of a collector zone and surrounding insulation zonesare produced on a monocrystal substrate layer, and a monocrystal seriesof layers is deposited over the collector zone, characterized in that,during the deposition by setting up suitable deposition conditions theamorphous or polycrystal layer is deposited on the insulator zone ingreater thickness than an epitaxial layer in the active transistor zone,where the differential epitaxy for the deposition of the monocrystalseries of layers in the emitter zone and of a polycrystal or amorphousseries of layers on the insulator zone begins with the creation of apart of a buffer layer on the insulator zone at a very low temperature,and further deposition of the buffer layer continues at a highertemperature.
 2. The procedure according to claim 1, characterized inthat the first part of the buffer layer consisting of Si is produced onthe insulator zone at a temperature in the range 450° C. to 700° C. 3.The procedure according to claim 2, characterized in that the first partof the buffer layer is produced on the. insulator zone at a temperatureof 550° C.
 4. The procedure according to claim 1, characterized in thatthe first part of the buffer layer is produced on the insulator zone ata temperature of 550° C.
 5. The procedure according to claim 1,characterized in that after the creation of the first part of the bufferlayer, the deposition continues at a higher temperature in the range of600° C. to 800° C.
 6. The procedure according to claim 2, characterizedin that after the creation of the first part of the buffer layer, thedeposition continues at a higher temperature in the range of 600° C. to800° C.
 7. The procedure according to claim 6, characterized in thatafter the creation of the first part of the buffer layer, the depositioncontinues at a temperature of 650° C.
 8. The procedure according toclaim 1, characterized in that after the creation of the first part ofthe buffer layer, the deposition continues at a temperature of 650° C.9. The procedure according to claim 3, characterized in that after thecreation of the first part of the buffer layer, the deposition continuesat a higher temperature in the range of 600° C. to 800° C.
 10. Theprocedure according to claim 9, characterized in that after the creationof the first part of the buffer layer, the deposition continues at atemperature of 650° C.
 11. The procedure according to claim 4,characterized in that after the creation of the first part of the bufferlayer, the deposition continues at a higher temperature in the range of600° C. to 800° C.
 12. The procedure according to claim 11,characterized in that after the creation of the first part of the bufferlayer, the deposition continues at a temperature of 650° C.